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HomeGADGETSELECTRONICSAffordable and Comprehensive Design-for-Test of 3D Stacking Die Devices

Affordable and Comprehensive Design-for-Test of 3D Stacking Die Devices

The semiconductor industry has made great strides in ASIC technology over the last 40 years, leading to better performance. But as Moore’s law nears its limits, scaling devices is becoming harder. Shrinking devices now takes longer, costs more, and presents challenges in technology, design, analysis, and manufacturing.

Developers of high-end semiconductor products that face manufacturing limitations with respect to die sizes are investing in 3D stacked die technology. These advanced designs already push current design-for-test solutions to the limits: tool run time, on-chip area demand, test pattern count, and test time. As design size and complexity continue to increase dramatically, we also see fewer I/Os available for 2D package test access. The result of fewer test IOs and larger die sizes is a significant increase in demand for test generation compute resources. These factors further combine to stress coverage, yield, power, and interconnect testing requirements.

How then, can designers manage design-for-test (DFT) for 3D stacked die devices?

The next major step for improving system-in-package (SiP) technology is 3D die stacking and packaging. 3D die stacking and packaging is the next big step for improving SiP technology. There are multiple methods of 3D die stacking, but the common goal is to use smaller, high-yield dies that are vertically stacked. This strategy alleviated many of the test challenges for large 2D or 2.5D devices. The highest quality known-good-die (KGD) testing is recommended for wafer probe testing of dies that will be assembled in a 3D stack. KGD test usually includes all package tests, except the interconnect tests between dies. Then, package test requires die-to-die (D2D) interconnect testing and reruns of KGD tests to make sure no defects were introduced during packaging and assembly. Fault diagnosis is required for each level of 3D testing, including full package-level stack diagnosis.

In this white paper, we describe a detailed implementation of the IEEE 1838-based DFT solution for 3D stacked die devices that covers all aspects of DFT—logic and memory testing of dies at wafer and stack level, testing between the dies in the stack, and diagnosis. Conceptually, the 3D DFT solution is a natural extension of a 2D, hierarchical DFT solution, adding one more level of hierarchy. All solutions needed for our 1838-based 3D implementation were already available: IJTAG for the serial access network, Tessent SSN for the FPP of 1838, and Tessent hierarchical, layout-aware diagnosis for logic and memories.

 

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